Optimization of CMOS Low Power High Speed Dual Edge Triggered Flip Flop

In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. The use of dual edge-triggered flip-flops can help reduce the clock frequency to half of the single edge-triggered flip-flops while maintaining the same data throughput, this thereafter translates to better performance in terms of both power dissipation and speed. Pulsetriggered flip-flops employ time borrowing across cycle boundaries which results in zero or negative setup time. Moreover, the pulse generator can be shared among many flip-flops to reduce the power dissipation and chip area. Pulse generator provides a narrow window to the latching stage during which the flip-flop is in the transparent mode. By reducing this pulse width, the setup time and hold time of the flip-flop are reduced. In this thesis, two dual-edge triggered D flip-flops are designed using master slave approach and pulsed latch approach respectively. One offers high performance while another offers clock skew tolerance. Comparing to other flip-flops in the latest publications, the Clock-to-Qdelay, setup time, hold time and power consumption of this flipflop are all smaller. In addition to this the proposed design consists of 15 transistors only and thus requires lesser overall silicon area. The result of thesimulation demonstrates that this dual-edge triggered flip-flop is a viable means toimprove design performance and to ease the strict and tight timing budget.